The integrated Field Programmable Gate Array (FPGA)-in-the-loop (FIL) workflow with MathWorks’ HDL Coder™ and HDL Verifier™ enables clients to automatically generate test benches for Hardware Description Language (HDL) verification, including VHSIC Hardware Description Language (VHDL) and Verilog, providing rapid prototyping and verification of designs.
The workflow is now available in R2020A MATLAB® release with Microchip Libero SoC v12.0. This enables the client to integrate MathWorks’ MATLAB, a multi-paradigm numerical computing environment, and MathWorks’ Simulink®, a graphical programming environment, with Microchip’s RTG4 development kit for FIL verification.
To execute this workflow, customers will require the following software tools:
Microchip (Libero SoC v12.0)
Hardware Support Package for RTG4
- Hardware support package from MathWorks or
- From within MATLAB Add On > Get Hardware Support Package option
Along with the software tools previously listed, customers will require the following hardware:
- Microchip’s RTG4 development kit
- Ethernet cable
- USB JTAG Cable – Programming the RTG4 kit
Once the tools are installed, set up the Libero tool path in MATLAB by invoking the hdlsetuptoolpath command from the MATLAB prompt and set the path to the Libero installer.
From the system block diagram within Simulink design for integrating RTG4 development kit in Libero, in the HDL Workflow Advisor window, select FPGA-in-the-Loop from the Target workflow drop-drop down list to enable the call to Libero. Then select Microsemi RTG4 FPGA from the Target platform drop-down list as shown in Figure 1.
The HDL Workflow Advisor from MathWorks is a guided tool that helps the designer generate the HDL code with HDL Coder and deploy the bitstream directly on the Microchip’s RTG4 board. The designer can then connect these boards directly with MATLAB and Simulink System Level Testbenches using HDL Verifier. This FIL simulation helps engineers in validating mission-critical systems for space and other applications directly on the RTG4 FPGA in one unified environment.
Microchip’s integrated FIL workflow with MathWorks enables a unified workflow to verify designs comprehensively. It integrates Microchip’s Libero SoC Design Suite—a comprehensive, easy-to-learn, easy-to-adopt development toolset for designing with Microchip's FPGAs—with MATLAB and Simulink for design verification and provides FIL verification with Microchip FPGA boards. This helps clients catch bugs early in the design cycle, and in turn, reduces time to market and enables early verification.
Watch the “Targeting Algorithms to Microsemi FPGAs using MATLAB and Simulink” webinar to see how MATLAB and Simulink are used to model, simulate, and verify algorithms targeted to Microchip FPGA boards.